// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    :
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/8/24
// Version      :  V 1.0 
// 
//Abstract      :
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 
//  
// *********************************************************************
// `include "top_define.v"
// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
// DESCRIPTION
// *******************
// 
// 
//*******************
//DEFINE(s)
//*******************
//`define UDLY 1    //Unit delay, for non-blocking assignments in sequential logic

//*******************
//DEFINE MODULE PORT
module schedule_threshold_interface(
    input  wire       clk                     , 
    input  wire       rst_n                   ,
    //******************************************************************
    //cpu_interface
    //******************************************************************
    //队列&结点门限
    input  wire [ 5:0]  queue_node_pri_que_max_thr_dpram_addr       ,
    input  wire         queue_node_pri_que_max_thr_dpram_wen        ,
    input  wire [31:0]  queue_node_pri_que_max_thr_dpram_wdata      ,
    input  wire         queue_node_pri_que_max_thr_dpram_ren        ,
    output reg  [31:0]  queue_node_pri_que_max_thr_dpram_rdata      ,
    input  wire [ 2:0]  queue_node_pri_que_max_min_thr_dpram_addr   ,
    input  wire         queue_node_pri_que_max_min_thr_dpram_wen    ,
    input  wire [31:0]  queue_node_pri_que_max_min_thr_dpram_wdata  ,
    input  wire         queue_node_pri_que_max_min_thr_dpram_ren    ,
    output reg  [31:0]  queue_node_pri_que_max_min_thr_dpram_rdata  ,
    
    //******************************************************************
    //queue_shedule interface
    //******************************************************************
    //  enqueue
    input  wire [ 2:0]  query_CPU_node_minmax_threshold ,  //节点最小最大门限
    output reg  [31:0]  CPU_node_minmax_threshold_data  ,
    input  wire [ 5:0]  query_CPU_queue_max_threshold   ,  //队列最大门限
    output reg  [31:0]  CPU_queue_max_threshold_data    ,
    // output reg  [31:0]  CPU_BD_public_length            ,  //BD共享区大小
    //  dequeue
    input  wire [ 2:0]  query_CPU_node_min_threshold    ,
    output reg  [31:0]  CPU_node_min_threshold_data     

    );


//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS
    reg [31:0]  CPU_node_minmax_threshold_node0   ;
    reg [31:0]  CPU_node_minmax_threshold_node1   ;
    reg [31:0]  CPU_node_minmax_threshold_node2   ;
    reg [31:0]  CPU_node_minmax_threshold_node3   ;
    reg [31:0]  CPU_node_minmax_threshold_node4   ;
    
    reg [31:0]  query_CPU_queue_max_node0_pri0    ;
    reg [31:0]  query_CPU_queue_max_node0_pri1    ;
    reg [31:0]  query_CPU_queue_max_node0_pri2    ;
    reg [31:0]  query_CPU_queue_max_node0_pri3    ;
    reg [31:0]  query_CPU_queue_max_node0_pri4    ;
    reg [31:0]  query_CPU_queue_max_node0_pri5    ;
    reg [31:0]  query_CPU_queue_max_node0_pri6    ;
    reg [31:0]  query_CPU_queue_max_node0_pri7    ;

    reg [31:0]  query_CPU_queue_max_node1_pri0    ;
    reg [31:0]  query_CPU_queue_max_node1_pri1    ;
    reg [31:0]  query_CPU_queue_max_node1_pri2    ;
    reg [31:0]  query_CPU_queue_max_node1_pri3    ;
    reg [31:0]  query_CPU_queue_max_node1_pri4    ;
    reg [31:0]  query_CPU_queue_max_node1_pri5    ;
    reg [31:0]  query_CPU_queue_max_node1_pri6    ;
    reg [31:0]  query_CPU_queue_max_node1_pri7    ;

    reg [31:0]  query_CPU_queue_max_node2_pri0    ;
    reg [31:0]  query_CPU_queue_max_node2_pri1    ;
    reg [31:0]  query_CPU_queue_max_node2_pri2    ;
    reg [31:0]  query_CPU_queue_max_node2_pri3    ;
    reg [31:0]  query_CPU_queue_max_node2_pri4    ;
    reg [31:0]  query_CPU_queue_max_node2_pri5    ;
    reg [31:0]  query_CPU_queue_max_node2_pri6    ;
    reg [31:0]  query_CPU_queue_max_node2_pri7    ;

    reg [31:0]  query_CPU_queue_max_node3_pri0    ;
    reg [31:0]  query_CPU_queue_max_node3_pri1    ;
    reg [31:0]  query_CPU_queue_max_node3_pri2    ;
    reg [31:0]  query_CPU_queue_max_node3_pri3    ;
    reg [31:0]  query_CPU_queue_max_node3_pri4    ;
    reg [31:0]  query_CPU_queue_max_node3_pri5    ;
    reg [31:0]  query_CPU_queue_max_node3_pri6    ;
    reg [31:0]  query_CPU_queue_max_node3_pri7    ;

    reg [31:0]  query_CPU_queue_max_node4    ;

//WIRES
    wire [2:0] node_wr_select;
    wire [2:0] node_rd_select;
    wire [5:0] queue_wr_select;
    wire [5:0] queue_rd_select;
 //*********************
//MAIN CORE
//*********************
assign node_rd_select = (queue_node_pri_que_max_min_thr_dpram_ren)? queue_node_pri_que_max_min_thr_dpram_addr : 3'b111;
//NODE threshold read
always @(posedge clk or negedge rst_n) begin : cpu_read_node_min_max_threshold
    if (~rst_n) begin
        // reset
        queue_node_pri_que_max_min_thr_dpram_rdata <= 32'b0;
    end
    else if (node_rd_select == 3'd0) begin
        queue_node_pri_que_max_min_thr_dpram_rdata <= CPU_node_minmax_threshold_node0;
    end
    else if (node_rd_select == 3'd1) begin
        queue_node_pri_que_max_min_thr_dpram_rdata <= CPU_node_minmax_threshold_node1;
    end
    else if (node_rd_select == 3'd2) begin
        queue_node_pri_que_max_min_thr_dpram_rdata <= CPU_node_minmax_threshold_node2;
    end
    else if (node_rd_select == 3'd3) begin
        queue_node_pri_que_max_min_thr_dpram_rdata <= CPU_node_minmax_threshold_node3;
    end
    else if (node_rd_select == 3'd4) begin
        queue_node_pri_que_max_min_thr_dpram_rdata <= CPU_node_minmax_threshold_node4;
    end
    else begin
        queue_node_pri_que_max_min_thr_dpram_rdata <= queue_node_pri_que_max_min_thr_dpram_rdata;
    end
end
// NODE threshold query
always @(posedge clk or negedge rst_n) begin : node_min_max_threshold_query
    if (~rst_n) begin
        // reset
        CPU_node_minmax_threshold_data <= 32'b0;
    end
    else if (query_CPU_node_minmax_threshold == 3'd0) begin
        CPU_node_minmax_threshold_data <= CPU_node_minmax_threshold_node0;
    end
    else if (query_CPU_node_minmax_threshold == 3'd1) begin
        CPU_node_minmax_threshold_data <= CPU_node_minmax_threshold_node1;
    end
    else if (query_CPU_node_minmax_threshold == 3'd2) begin
        CPU_node_minmax_threshold_data <= CPU_node_minmax_threshold_node2;
    end
    else if (query_CPU_node_minmax_threshold == 3'd3) begin
        CPU_node_minmax_threshold_data <= CPU_node_minmax_threshold_node3;
    end
    else if (query_CPU_node_minmax_threshold == 3'd4) begin
        CPU_node_minmax_threshold_data <= CPU_node_minmax_threshold_node4;
    end
    else begin
        CPU_node_minmax_threshold_data <= CPU_node_minmax_threshold_data;
    end
end

always @(posedge clk or negedge rst_n) begin : node_min_threshold_query
    if (~rst_n) begin
        // reset
        CPU_node_min_threshold_data <= 32'b0;
    end
    else if (query_CPU_node_min_threshold == 3'd0) begin
        CPU_node_min_threshold_data <= {16'd0,CPU_node_minmax_threshold_node0[31:16]};
    end
    else if (query_CPU_node_min_threshold == 3'd1) begin
        CPU_node_min_threshold_data <= {16'd0,CPU_node_minmax_threshold_node1[31:16]};
    end
    else if (query_CPU_node_min_threshold == 3'd2) begin
        CPU_node_min_threshold_data <= {16'd0,CPU_node_minmax_threshold_node2[31:16]};
    end
    else if (query_CPU_node_min_threshold == 3'd3) begin
        CPU_node_min_threshold_data <= {16'd0,CPU_node_minmax_threshold_node3[31:16]};
    end
    else if (query_CPU_node_min_threshold == 3'd4) begin
        CPU_node_min_threshold_data <= {16'd0,CPU_node_minmax_threshold_node4[31:16]};
    end
    else begin
        CPU_node_min_threshold_data <= CPU_node_min_threshold_data;
    end
end

// NODE threshold update
assign  node_wr_select = (queue_node_pri_que_max_min_thr_dpram_wen)? queue_node_pri_que_max_min_thr_dpram_addr : 3'b111;
always @(posedge clk or negedge rst_n) begin : node_0_threshold_update
    if (~rst_n) begin
        // reset
        CPU_node_minmax_threshold_node0 <= 32'b0;
    end
    else if (node_wr_select == 3'd0) begin
        CPU_node_minmax_threshold_node0 <= queue_node_pri_que_max_min_thr_dpram_wdata;
    end
    else begin
        CPU_node_minmax_threshold_node0 <= CPU_node_minmax_threshold_node0;
    end
end

always @(posedge clk or negedge rst_n) begin : node_1_threshold_update
    if (~rst_n) begin
        // reset
        CPU_node_minmax_threshold_node1 <= 32'b0;
    end
    else if (node_wr_select == 3'd1) begin
        CPU_node_minmax_threshold_node1 <= queue_node_pri_que_max_min_thr_dpram_wdata;
    end
    else begin
        CPU_node_minmax_threshold_node1 <= CPU_node_minmax_threshold_node1;
    end
end

always @(posedge clk or negedge rst_n) begin : node_2_threshold_update
    if (~rst_n) begin
        // reset
        CPU_node_minmax_threshold_node2 <= 32'b0;
    end
    else if (node_wr_select == 3'd2) begin
        CPU_node_minmax_threshold_node2 <= queue_node_pri_que_max_min_thr_dpram_wdata;
    end
    else begin
        CPU_node_minmax_threshold_node2 <= CPU_node_minmax_threshold_node2;
    end
end

always @(posedge clk or negedge rst_n) begin : node_3_threshold_update
    if (~rst_n) begin
        // reset
        CPU_node_minmax_threshold_node3 <= 32'b0;
    end
    else if (node_wr_select == 3'd3) begin
        CPU_node_minmax_threshold_node3 <= queue_node_pri_que_max_min_thr_dpram_wdata;
    end
    else begin
        CPU_node_minmax_threshold_node3 <= CPU_node_minmax_threshold_node3;
    end
end

always @(posedge clk or negedge rst_n) begin : node_4_threshold_update
    if (~rst_n) begin
        // reset
        CPU_node_minmax_threshold_node4 <= 32'b0;
    end
    else if (node_wr_select == 3'd4) begin
        CPU_node_minmax_threshold_node4 <= queue_node_pri_que_max_min_thr_dpram_wdata;
    end
    else begin
        CPU_node_minmax_threshold_node4 <= CPU_node_minmax_threshold_node4;
    end
end

//queue_threshold_query
always @(posedge clk or negedge rst_n) begin : queue_max_threshold_query
    if (~rst_n) begin
        // reset
        CPU_queue_max_threshold_data <= 32'b0;
    end
    else if (query_CPU_queue_max_threshold == 6'd0) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node0_pri0;
    end
    else if (query_CPU_queue_max_threshold == 6'd1) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node0_pri1;
    end
    else if (query_CPU_queue_max_threshold == 6'd2) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node0_pri2;
    end
    else if (query_CPU_queue_max_threshold == 6'd3) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node0_pri3;
    end
    else if (query_CPU_queue_max_threshold == 6'd4) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node0_pri4;
    end
    else if (query_CPU_queue_max_threshold == 6'd5) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node0_pri5;
    end
    else if (query_CPU_queue_max_threshold == 6'd6) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node0_pri6;
    end
    else if (query_CPU_queue_max_threshold == 6'd7) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node0_pri7;
    end
    else if (query_CPU_queue_max_threshold == 6'd8) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node1_pri0;
    end
    else if (query_CPU_queue_max_threshold == 6'd9) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node1_pri1;
    end
    else if (query_CPU_queue_max_threshold == 6'd10) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node1_pri2;
    end
    else if (query_CPU_queue_max_threshold == 6'd11) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node1_pri3;
    end
    else if (query_CPU_queue_max_threshold == 6'd12) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node1_pri4;
    end
    else if (query_CPU_queue_max_threshold == 6'd13) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node1_pri5;
    end
    else if (query_CPU_queue_max_threshold == 6'd14) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node1_pri6;
    end
    else if (query_CPU_queue_max_threshold == 6'd15) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node1_pri7;
    end
    else if (query_CPU_queue_max_threshold == 6'd16) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node2_pri0;
    end
    else if (query_CPU_queue_max_threshold == 6'd17) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node2_pri1;
    end
    else if (query_CPU_queue_max_threshold == 6'd18) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node2_pri2;
    end
    else if (query_CPU_queue_max_threshold == 6'd19) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node2_pri3;
    end
    else if (query_CPU_queue_max_threshold == 6'd20) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node2_pri4;
    end
    else if (query_CPU_queue_max_threshold == 6'd21) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node2_pri5;
    end
    else if (query_CPU_queue_max_threshold == 6'd22) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node2_pri6;
    end
    else if (query_CPU_queue_max_threshold == 6'd23) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node2_pri7;
    end
    else if (query_CPU_queue_max_threshold == 6'd24) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node3_pri0;
    end
    else if (query_CPU_queue_max_threshold == 6'd25) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node3_pri1;
    end
    else if (query_CPU_queue_max_threshold == 6'd26) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node3_pri2;
    end
    else if (query_CPU_queue_max_threshold == 6'd27) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node3_pri3;
    end
    else if (query_CPU_queue_max_threshold == 6'd28) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node3_pri4;
    end
    else if (query_CPU_queue_max_threshold == 6'd29) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node3_pri5;
    end
    else if (query_CPU_queue_max_threshold == 6'd30) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node3_pri6;
    end
    else if (query_CPU_queue_max_threshold == 6'd31) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node3_pri7;
    end
    else if (query_CPU_queue_max_threshold == 6'd32) begin
        CPU_queue_max_threshold_data <= query_CPU_queue_max_node4;
    end
    else begin
        CPU_queue_max_threshold_data <= CPU_queue_max_threshold_data;
    end
end
assign  queue_wr_select = (queue_node_pri_que_max_thr_dpram_wen)? queue_node_pri_que_max_thr_dpram_addr : 6'b11_1111;
assign  queue_rd_select = (queue_node_pri_que_max_thr_dpram_ren)? queue_node_pri_que_max_thr_dpram_addr : 6'b11_1111;
//queue_threshold_read
always @(posedge clk or negedge rst_n) begin : read_queue_max_threshold
    if (~rst_n) begin
        // reset
        queue_node_pri_que_max_thr_dpram_rdata <= 32'b0;
    end
    else if (queue_rd_select == 6'd0) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node0_pri0;
    end
    else if (queue_rd_select == 6'd1) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node0_pri1;
    end
    else if (queue_rd_select == 6'd2) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node0_pri2;
    end
    else if (queue_rd_select == 6'd3) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node0_pri3;
    end
    else if (queue_rd_select == 6'd4) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node0_pri4;
    end
    else if (queue_rd_select == 6'd5) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node0_pri5;
    end
    else if (queue_rd_select == 6'd6) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node0_pri6;
    end
    else if (queue_rd_select == 6'd7) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node0_pri7;
    end
    else if (queue_rd_select == 6'd8) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node1_pri0;
    end
    else if (queue_rd_select == 6'd9) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node1_pri1;
    end
    else if (queue_rd_select == 6'd10) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node1_pri2;
    end
    else if (queue_rd_select == 6'd11) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node1_pri3;
    end
    else if (queue_rd_select == 6'd12) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node1_pri4;
    end
    else if (queue_rd_select == 6'd13) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node1_pri5;
    end
    else if (queue_rd_select == 6'd14) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node1_pri6;
    end
    else if (queue_rd_select == 6'd15) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node1_pri7;
    end
    else if (queue_rd_select == 6'd16) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node2_pri0;
    end
    else if (queue_rd_select == 6'd17) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node2_pri1;
    end
    else if (queue_rd_select == 6'd18) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node2_pri2;
    end
    else if (queue_rd_select == 6'd19) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node2_pri3;
    end
    else if (queue_rd_select == 6'd20) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node2_pri4;
    end
    else if (queue_rd_select == 6'd21) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node2_pri5;
    end
    else if (queue_rd_select == 6'd22) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node2_pri6;
    end
    else if (queue_rd_select == 6'd23) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node2_pri7;
    end
    else if (queue_rd_select == 6'd24) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node3_pri0;
    end
    else if (queue_rd_select == 6'd25) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node3_pri1;
    end
    else if (queue_rd_select == 6'd26) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node3_pri2;
    end
    else if (queue_rd_select == 6'd27) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node3_pri3;
    end
    else if (queue_rd_select == 6'd28) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node3_pri4;
    end
    else if (queue_rd_select == 6'd29) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node3_pri5;
    end
    else if (queue_rd_select == 6'd30) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node3_pri6;
    end
    else if (queue_rd_select == 6'd31) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node3_pri7;
    end
    else if (queue_rd_select == 6'd32) begin
        queue_node_pri_que_max_thr_dpram_rdata <= query_CPU_queue_max_node4;
    end
    else begin
        queue_node_pri_que_max_thr_dpram_rdata <= queue_node_pri_que_max_thr_dpram_rdata;
    end
end

//queue_threshold_update
always @(posedge clk or negedge rst_n) begin : node_0_pri_0_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node0_pri0 <= 32'b0;
    end
    else if (queue_wr_select == 6'd0) begin
        query_CPU_queue_max_node0_pri0 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node0_pri0 <= query_CPU_queue_max_node0_pri0;
    end
end
always @(posedge clk or negedge rst_n) begin : node_0_pri_1_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node0_pri1 <= 32'b0;
    end
    else if (queue_wr_select == 6'd1) begin
        query_CPU_queue_max_node0_pri1 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node0_pri1 <= query_CPU_queue_max_node0_pri1;
    end
end
always @(posedge clk or negedge rst_n) begin : node_0_pri_2_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node0_pri2 <= 32'b0;
    end
    else if (queue_wr_select == 6'd2) begin
        query_CPU_queue_max_node0_pri2 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node0_pri2 <= query_CPU_queue_max_node0_pri2;
    end
end
always @(posedge clk or negedge rst_n) begin : node_0_pri_3_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node0_pri3 <= 32'b0;
    end
    else if (queue_wr_select == 6'd3) begin
        query_CPU_queue_max_node0_pri3 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node0_pri3 <= query_CPU_queue_max_node0_pri3;
    end
end
always @(posedge clk or negedge rst_n) begin : node_0_pri_4_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node0_pri4 <= 32'b0;
    end
    else if (queue_wr_select == 6'd4) begin
        query_CPU_queue_max_node0_pri4 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node0_pri4 <= query_CPU_queue_max_node0_pri4;
    end
end
always @(posedge clk or negedge rst_n) begin : node_0_pri_5_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node0_pri5 <= 32'b0;
    end
    else if (queue_wr_select == 6'd5) begin
        query_CPU_queue_max_node0_pri5 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node0_pri5 <= query_CPU_queue_max_node0_pri5;
    end
end
always @(posedge clk or negedge rst_n) begin : node_0_pri_6_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node0_pri6 <= 32'b0;
    end
    else if (queue_wr_select == 6'd6) begin
        query_CPU_queue_max_node0_pri6 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node0_pri6 <= query_CPU_queue_max_node0_pri6;
    end
end
always @(posedge clk or negedge rst_n) begin : node_0_pri_7_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node0_pri7 <= 32'b0;
    end
    else if (queue_wr_select == 6'd7) begin
        query_CPU_queue_max_node0_pri7 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node0_pri7 <= query_CPU_queue_max_node0_pri7;
    end
end

always @(posedge clk or negedge rst_n) begin : node_1_pri_0_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node1_pri0 <= 32'b0;
    end
    else if (queue_wr_select == 6'd8) begin
        query_CPU_queue_max_node1_pri0 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node1_pri0 <= query_CPU_queue_max_node1_pri0;
    end
end
always @(posedge clk or negedge rst_n) begin : node_1_pri_1_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node1_pri1 <= 32'b0;
    end
    else if (queue_wr_select == 6'd9) begin
        query_CPU_queue_max_node1_pri1 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node1_pri1 <= query_CPU_queue_max_node1_pri1;
    end
end
always @(posedge clk or negedge rst_n) begin : node_1_pri_2_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node1_pri2 <= 32'b0;
    end
    else if (queue_wr_select == 6'd10) begin
        query_CPU_queue_max_node1_pri2 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node1_pri2 <= query_CPU_queue_max_node1_pri2;
    end
end
always @(posedge clk or negedge rst_n) begin : node_1_pri_3_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node1_pri3 <= 32'b0;
    end
    else if (queue_wr_select == 6'd11) begin
        query_CPU_queue_max_node1_pri3 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node1_pri3 <= query_CPU_queue_max_node1_pri3;
    end
end
always @(posedge clk or negedge rst_n) begin : node_1_pri_4_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node1_pri4 <= 32'b0;
    end
    else if (queue_wr_select == 6'd12) begin
        query_CPU_queue_max_node1_pri4 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node1_pri4 <= query_CPU_queue_max_node1_pri4;
    end
end
always @(posedge clk or negedge rst_n) begin : node_1_pri_5_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node1_pri5 <= 32'b0;
    end
    else if (queue_wr_select == 6'd13) begin
        query_CPU_queue_max_node1_pri5 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node1_pri5 <= query_CPU_queue_max_node1_pri5;
    end
end
always @(posedge clk or negedge rst_n) begin : node_1_pri_6_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node1_pri6 <= 32'b0;
    end
    else if (queue_wr_select == 6'd14) begin
        query_CPU_queue_max_node1_pri6 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node1_pri6 <= query_CPU_queue_max_node1_pri6;
    end
end
always @(posedge clk or negedge rst_n) begin : node_1_pri_7_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node1_pri7 <= 32'b0;
    end
    else if (queue_wr_select == 6'd15) begin
        query_CPU_queue_max_node1_pri7 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node1_pri7 <= query_CPU_queue_max_node1_pri7;
    end
end

always @(posedge clk or negedge rst_n) begin : node_2_pri_0_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node2_pri0 <= 32'b0;
    end
    else if (queue_wr_select == 6'd16) begin
        query_CPU_queue_max_node2_pri0 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node2_pri0 <= query_CPU_queue_max_node2_pri0;
    end
end
always @(posedge clk or negedge rst_n) begin : node_2_pri_1_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node2_pri1 <= 32'b0;
    end
    else if (queue_wr_select == 6'd17) begin
        query_CPU_queue_max_node2_pri1 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node2_pri1 <= query_CPU_queue_max_node2_pri1;
    end
end
always @(posedge clk or negedge rst_n) begin : node_2_pri_2_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node2_pri2 <= 32'b0;
    end
    else if (queue_wr_select == 6'd18) begin
        query_CPU_queue_max_node2_pri2 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node2_pri2 <= query_CPU_queue_max_node2_pri2;
    end
end
always @(posedge clk or negedge rst_n) begin : node_2_pri_3_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node2_pri3 <= 32'b0;
    end
    else if (queue_wr_select == 6'd19) begin
        query_CPU_queue_max_node2_pri3 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node2_pri3 <= query_CPU_queue_max_node2_pri3;
    end
end
always @(posedge clk or negedge rst_n) begin : node_2_pri_4_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node2_pri4 <= 32'b0;
    end
    else if (queue_wr_select == 6'd20) begin
        query_CPU_queue_max_node2_pri4 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node2_pri4 <= query_CPU_queue_max_node2_pri4;
    end
end
always @(posedge clk or negedge rst_n) begin : node_2_pri_5_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node2_pri5 <= 32'b0;
    end
    else if (queue_wr_select == 6'd21) begin
        query_CPU_queue_max_node2_pri5 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node2_pri5 <= query_CPU_queue_max_node2_pri5;
    end
end
always @(posedge clk or negedge rst_n) begin : node_2_pri_6_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node2_pri6 <= 32'b0;
    end
    else if (queue_wr_select == 6'd22) begin
        query_CPU_queue_max_node2_pri6 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node2_pri6 <= query_CPU_queue_max_node2_pri6;
    end
end
always @(posedge clk or negedge rst_n) begin : node_2_pri_7_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node2_pri7 <= 32'b0;
    end
    else if (queue_wr_select == 6'd23) begin
        query_CPU_queue_max_node2_pri7 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node2_pri7 <= query_CPU_queue_max_node2_pri7;
    end
end

always @(posedge clk or negedge rst_n) begin : node_3_pri_0_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node3_pri0 <= 32'b0;
    end
    else if (queue_wr_select == 6'd24) begin
        query_CPU_queue_max_node3_pri0 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node3_pri0 <= query_CPU_queue_max_node3_pri0;
    end
end
always @(posedge clk or negedge rst_n) begin : node_3_pri_1_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node3_pri1 <= 32'b0;
    end
    else if (queue_wr_select == 6'd25) begin
        query_CPU_queue_max_node3_pri1 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node3_pri1 <= query_CPU_queue_max_node3_pri1;
    end
end
always @(posedge clk or negedge rst_n) begin : node_3_pri_2_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node3_pri2 <= 32'b0;
    end
    else if (queue_wr_select == 6'd26) begin
        query_CPU_queue_max_node3_pri2 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node3_pri2 <= query_CPU_queue_max_node3_pri2;
    end
end
always @(posedge clk or negedge rst_n) begin : node_3_pri_3_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node3_pri3 <= 32'b0;
    end
    else if (queue_wr_select == 6'd27) begin
        query_CPU_queue_max_node3_pri3 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node3_pri3 <= query_CPU_queue_max_node3_pri3;
    end
end
always @(posedge clk or negedge rst_n) begin : node_3_pri_4_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node3_pri4 <= 32'b0;
    end
    else if (queue_wr_select == 6'd28) begin
        query_CPU_queue_max_node3_pri4 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node3_pri4 <= query_CPU_queue_max_node3_pri4;
    end
end
always @(posedge clk or negedge rst_n) begin : node_3_pri_5_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node3_pri5 <= 32'b0;
    end
    else if (queue_wr_select == 6'd29) begin
        query_CPU_queue_max_node3_pri5 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node3_pri5 <= query_CPU_queue_max_node3_pri5;
    end
end
always @(posedge clk or negedge rst_n) begin : node_3_pri_6_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node3_pri6 <= 32'b0;
    end
    else if (queue_wr_select == 6'd30) begin
        query_CPU_queue_max_node3_pri6 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node3_pri6 <= query_CPU_queue_max_node3_pri6;
    end
end
always @(posedge clk or negedge rst_n) begin : node_3_pri_7_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node3_pri7 <= 32'b0;
    end
    else if (queue_wr_select == 6'd31) begin
        query_CPU_queue_max_node3_pri7 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node3_pri7 <= query_CPU_queue_max_node3_pri7;
    end
end

always @(posedge clk or negedge rst_n) begin : node_3_pri_8_threshold_update
    if (~rst_n) begin
        // reset
        query_CPU_queue_max_node4 <= 32'b0;
    end
    else if (queue_wr_select == 6'd32) begin
        query_CPU_queue_max_node4 <= queue_node_pri_que_max_thr_dpram_wdata;
    end
    else begin
        query_CPU_queue_max_node4 <= query_CPU_queue_max_node4;
    end
end

endmodule
